A novel MIMO-OFDM Alamouti architecture for 5G systems at 26 GHz

Abstract

This paper introduces a novel 5G Millimetre-wave (mmWave) real-time Multiple-Input Multiple-Output (MIMO) testbed architecture aimed to tackle the 5G communication requirements. In this context, a $2\times2$ Alamouti coder and decoder is implemented in the VC707 Field Programmable Gate Array (FPGA) development board and its logical resources usage compared to those in the literature. In order to reduce the Hardware (HW) footprint of the proposed MIMO - Orthogonal Frequency Division Multiplexing (OFDM) Alamouti system, a pipelined modular architecture is considered, in order to boost HW utilisation and performance of MIMO-OFDM systems. A single pair of Inverse Fast Fourier Transform (IFFT)/ Fast Fourier Transform (FFT) is enough to process data for each MIMO antenna path. The achieved results show the importance of FPGA resource optimisation, demonstrating how depend coding and modulation are to hardware resources. Moreover, a Radio Frequency (RF) architecture is proposed to address $2 \times2$ MIMO communications at 26 GHz.