Design of Synchronous NoC for High Speed Multiprocessor Environment

Abstract

As technology advances, processors are scale down size by reducing channel length. However, number of issues raises by scaling down of channel length. Network on Chip (NoC) is the supported communication protocol for System on Chip (SoC) and provides parallel communication among processing elements (PEs). Designing of synchronous NoC is quite complex as different parameters such as unbalanced traffic, buffer utilization affect the performance. This paper proposes an intra-inter buffer structure to support unbalance traffic. The proposed NoC router is able to configure channel dynamically depends on traffic conditions hence avoiding of Head of Line (HoL) error for data packet. The proposed NoC router is achieved approximately 45% more operating frequency when compared to traditional router.