Towards a Description Synthesis of the Entanglement of the Substrate with the Interconnection Network, for Fast Modeling of 3D RF circuits

A. Nabil, J. Bernardo, A. Rangel, M. Shaker, M. Abouelatta, L. Fakri-Bouchet, C. Gontrand
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Abstract

3D chip stacking is considered known to overcome conventional 2D-IC issues, using Trough Silicon Via (TSVs) to ensure vertical signal transmission between data.  If the electrical behaviour of 3D interconnections (redistribution metal lines and through silicon vias) used in 3D IC stack technologies are to be explored in this paper, the substrate itself is of interest, via Green Kernels by solving Poisson's equation analytically. Using this technique, the substrate coupling and loss in IC's can be analysed. We implement our algorithms in MATLAB. This method has been already used; but, it permits to extract impedances for a stacked uniform layers substrate. We have extended for any numbers of embedded contacts, of any shape. On a second hand, we grasp the background noise   between any two points, in the bulk, or at the surface, from a transfer impedance extraction technique.  With an analog algorithm, a strength of this work, we calculate unsteady solutions of the heat equation, using a spreading resistance concept. This method has been adapted to stacked layers. With this general tool of impedance field, we investigate on the problems encountered by interconnects, especially the vias, the substrate, and their entanglement. A calculation of thermal mechanical stresses and their effects on substrate crack (max and min stresses), devices (i.e: transistors) and hotspots, are made to track the performance. But, to well understand the interconnection incidence on 3D system performances, it is important to consider the whole electrical context; it seems relevant to consider the possible couplings between vias, not only by the electromagnetic field, but also by any possible energy transfer between interconnects; more generally, one of actual problem is to determine  where the energy is  really confined in such 3D circuits, before find solutions to limit  pollutions  coming from  electro-magneto -thermal   phenomena or  background noises.
基于互连网络的基片纠缠描述综合,用于三维射频电路的快速建模
3D芯片堆叠被认为可以克服传统的2D-IC问题,使用槽硅通孔(tsv)来确保数据之间的垂直信号传输。如果要在本文中探索3D IC堆栈技术中使用的3D互连(重新分配金属线和通过硅通孔)的电学行为,则基片本身是感兴趣的,通过绿色核通过解析解决泊松方程。利用该技术,可以分析集成电路中的衬底耦合和损耗。我们在MATLAB中实现我们的算法。这种方法已经被使用过;但是,它允许提取阻抗的堆叠均匀层的衬底。我们已经扩展了任何数量的嵌入式接触,任何形状。另一方面,通过传递阻抗提取技术,我们掌握了任意两点之间的背景噪声,无论是在整体上还是在表面上。利用模拟算法,利用扩展阻力的概念,我们计算了热方程的非定常解。该方法已适用于堆叠层。利用这个阻抗场的通用工具,我们研究了互连所遇到的问题,特别是过孔、衬底和它们的纠缠。计算热机械应力及其对衬底裂纹(最大和最小应力)、器件(即晶体管)和热点的影响,以跟踪性能。但是,为了更好地理解互连对三维系统性能的影响,重要的是要考虑整个电气环境;考虑通孔之间可能的耦合似乎是相关的,不仅通过电磁场,而且通过互连之间任何可能的能量传递;更一般地说,一个实际的问题是在找到解决方案来限制来自电磁热现象或背景噪音的污染之前,确定能量在这种3D电路中真正被限制在哪里。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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