A HW/SW Co-design of Execution Migration for Shared-ISA Heterogeneous Chip Multiprocessors

2013 IEEE Eighth International Conference on Networking, Architecture and Storage Pub Date : 2013-07-17 DOI:10.1109/NAS.2013.10

Hongwei Liu, Bo Sang, Jing Huang, Ji Qiu, Xiang Gao

引用次数: 0

Abstract

Heterogeneous multi-core processors have strong potential for performance improvement, energy efficiency and area efficiency, compared to the homogeneous multi-core processors. The present methods of execution migration for heterogeneous multi-core processor suffer in efficiency, cost, compatibility, or programmability. In this paper, we propose a HW/SW code sign migration method based on binary-instrumentation. Our method takes full advantage of the shared-ISA. It enhances the performance of heterogeneous chip multiprocessor with low HW/SW cost. And it's not required to modify source codes or compile system. The experiment results show that the efficiency of our method is 3.29 times of kernel simulation.

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共享isa异构芯片多处理器执行迁移的软硬件协同设计

与同质多核处理器相比，异构多核处理器在性能改进、能效和面积效率方面具有强大的潜力。目前异构多核处理器的执行迁移方法存在效率、成本、兼容性和可编程性等问题。本文提出了一种基于二进制检测的硬件/软件码号迁移方法。我们的方法充分利用了共享isa。它以较低的硬件/软件成本提高了异构芯片多处理器的性能。并且不需要修改源代码或编译系统。实验结果表明，该方法的效率是核仿真的3.29倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2013 IEEE Eighth International Conference on Networking, Architecture and Storage

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