High throughput FPGA architecture for corner detection in traffic images

Abstract

Corner detection is the most computationally intensive step in vehicle tracking and vehicle speed estimation algorithms. In order to have real-time vehicle tracking for traffic surveillance applications, high speed architectures for corner detection are needed. This paper presents a high throughput FPGA architecture for detecting special features (corners in more detail) on traffic images which are captured by cameras. The module is implemented based on the FAST (Features from Accelerated Segment Test) algorithm with some modifications to be suitable for traffic images. The proposed architecture is able to reduce a great number of unnecessary detected corner points and maintain a high throughput of more than a thousand of 8-bit gray-scale images per second at 640 × 480 resolution. The resource usage is 21% lower than that of existing work, which allows the architecture to be implemented on almost all types of FPGA.