Benchmarking of on-chip interconnection networks

Abstract

More complex on-chip interconnection structures such as networks on chip emerge today. As the number of interconnect architectures rises there is a need to do an impartial evaluation of the performance of the interconnect structure. This is important for both the designer of the interconnect as well as for the system designer in order to achieve best performance vs. cost tradeoff. The work presented in this paper describes a method to specify, execute, and evaluate benchmarks for on-chip interconnects. The benchmarking method uses formal traffic specifications together with architecture independent constraints to form the benchmark specification. This specification is adapted to the simulation flow available for the interconnect and simulated to get the wanted results. The benchmark method is evaluated using two related examples where throughput is the main focus in the results. These examples show the applicability of the method.