A component-based visual simulator for MIPS32 processors

Abstract

Processor implementation and performance analysis are fundamental in computer architecture education. A processor can be described at different abstraction levels: a black box with inputs and outputs, the composition of RT (Register-Transfer) level components, the composition of gate level components, etc. Performance of a processor is impacted by factors such as clock cycle, programs, and componentspsila propagation delays. With the traditional text-based educational material, teaching and learning of the processor implementation is difficult. Processor simulation offers an effective way for education through dynamic visualization and flexible experimentation. This paper presents a MIPS32 Processor Simulator that models the single-cycle, multi-cycle, and pipeline processors described in the classic textbook, ldquoComputer Organization and Design: The Hardware/Software Interfacerdquo written by Patterson and Hennessy. The Simulator is developed in DEVSJAVA simulator, a realization of the Discrete Event System Specification with support for modeling parallel, hierarchical, and component-based systems. This simulator provides animation at RT-level during instruction execution, collects performance data (including cycle count, execution time, and instruction count), allows viewing components at desired abstraction levels, and is platform independent. The simulator can also be easily extended/reused to develop other processor types. Existing MIPS processor simulators do not provide sufficient support for the above mentioned features.