G. Signorini, C. Siviero, S. Grivet-Talocia, I. Stievano
{"title":"Power and Signal Integrity co-simulation via compressed macromodels of high-speed transceivers","authors":"G. Signorini, C. Siviero, S. Grivet-Talocia, I. Stievano","doi":"10.1109/SAPIW.2015.7237385","DOIUrl":null,"url":null,"abstract":"This paper presents innovative compressed macro-models of high-speed digital transceivers for system-level Signal and Power Integrity co-simulations. These simulations assume a paramount importance for the design of modern, low-cost and highly integrated systems. An excellent accuracy and an outstanding run-time speed-up are demonstrated by applying the macromodeling methodology to a state-of-the-art I/O buffer for a low-power memory interface. Supply voltage variations and related effects on output transitions are accurately reproduced, enabling precise estimates of critical system-level timing margins.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SAPIW.2015.7237385","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
Abstract
This paper presents innovative compressed macro-models of high-speed digital transceivers for system-level Signal and Power Integrity co-simulations. These simulations assume a paramount importance for the design of modern, low-cost and highly integrated systems. An excellent accuracy and an outstanding run-time speed-up are demonstrated by applying the macromodeling methodology to a state-of-the-art I/O buffer for a low-power memory interface. Supply voltage variations and related effects on output transitions are accurately reproduced, enabling precise estimates of critical system-level timing margins.