Design Techniques and Modeling for 60GHz Applications With a 65nm-CMOS-RF Technology

Abstract

To exploit the unlicensed band at frequencies around 60 GHz, a certain number of design rules is considered. This paper highlights the difficulties to design a millimeter CMOS power amplifier (PA). A model of a compact inductor and interconnect lines is detailed. This model takes into account substrate and resistive parasitic. A 65 nm CMOS technology from STMicroelectronics has been used. Innovative techniques are implemented in the design of a power amplifier (PA) which is optimized to deliver the maximum linear output power. To obtain good performances in a small surface of silicon, it has been designed, with both lumped and distributed elements. The PA delivers a linear output power of 8.9 dBm with just an area of 0.48 mm*0.6 mm including pads.