BPCS steganography for data security using FPGA implementation

Abstract

There are several techniques to conceal the secret information inside Cover objects; steganography is the one of them. Steganography is the art of invisible communication by concealing information inside other information. Images are the most popular cover objects for steganography. The BPCS steganography which stands for bit-plane complexity segmentation is the technique to hide secret information in some other data (carrier) with better visual imperceptibility. This technique uses the “noise-like” regions in the bit planes of the cover image to hide secret data without deteriorating the image quality. With this technique we can hide 50-60% of secrete data in the cover image. To embed the secret information inside images requires intensive computations, and therefore, the technique is implemented in an FPGA to increase the processing speed. This work presents a hardware implementation of bit-plane complexity segmentation (BPCS) steganography technique in Xilinx Spartan 3E FPGA family. To access the bit wise data on FPGA Baud rate can cause the delay.