Low-Power Design of Pipeline A/D Converters

Abstract

In this paper, low-power design techniques of highspeed A/D converters are reviewed and discussed. Pipeline and parallel-pipeline architectures are treated as these are dominant architectures when required high sampling rate and high resolution with reasonable power dissipation. A power optimization of pipeline and parallel pipeline ADCs based on models of noise analysis and response time of a building block in the multiple-stage pipeline ADC is also presented. Finally, the theoretical minimum of required power in pipeline ADCs is discussed