14.4-GS/s, 5-bit, 50mW time-interleaved ADC with distributed track-and-hold and sampling instant synchronization for ADC-based SerDes

Abstract

A 14.4-GS/s 5-b ADC is designed in 40nm CMOS with eight time-interleaved channels of Flash/Successive-Approximation hybrid sub-ADCs each running at 1.6GS/s. A modified bootstrapped track-and-hold switch incorporates a global clock to synchronize the sampling instant of each individual sub-channel, therefore improving multi-phase alignment. Measurement results show that the ADC can achieve a peak SNDR of 26.5dB, consuming 49.4mW, leading to a FoM of 199fJ/conversion-step, in a core area less than 800μm by 500μm.