A High-Gain LNA with Differential Output for 60-GHz Radio

Abstract

This paper presents a balun less differential output LNA by accounting for various interconnect losses. The modified cascode, having current reuse and body biasing in the 1st stage of the LNA, achieved dc power consumption PDC < 13 mW. On the other hand, the 2nd stage employs a differential output for improved noise (NF < 6.0 dB) and linearity (IIP3 > 2.0 dBm) performances. Moreover, the optimized MOSFET transistors are used in the proposed design to achieve noise resistance ROPT close to 50 Ω required for power matching, with the rejection of image signal @50GHz by more than +60 dB without sacrificing the LNA performances. The inductors used in the design are realized in the IHP 0.13 µm SiGe BiCMOS process, where ground shielded and optimization under Keysight ADS EM environment to realize high-quality factor Q > 25. The proposed LNA design layout occupies a chip area of 0.52 mm2. Theoretically, predicted S-parameters of the LNA were found to overestimate the simulated results due to the simplified equivalent circuit used. By accounting layout area, a new Figure-of-Merit (FoM) involving key performances like S21, noise factor F, and dc power consumption PDC was proposed and found to be significantly higher for the proposed LNA than reported work in the same technology. All the results presented in this paper are verified using the full EM simulation. However, their experimental verifications are not included due to the limitation of experimental testing facilities at the authors' Institutes.