The Realization of the 1GHz Negative Logarithmic Function Based on the 0.35um AMS Technology

Abstract

This paper presents the realization of the 1GHz Negative Logarithmic Function (NLF) based on the 0.35um AMS technology. Firstly, it shows some interesting advance beyond Mitchell's approach with hardware implementation of a sequential architecture minimized in terms of gates and thus optimized for power and area sensitive application. Secondly, it introduces the realization of the NLF using combinational logic only. Lastly, it presents the realization of the physical layout using the second method based on 0.35um AMS technology with Silicon Ensemble software.