Multi-tera-bit/s switch based on burst transfer and independent shared buffers

Abstract

The paper introduces an ATM-switch architecture growable to multi-tera-bit/s. The main advantage of the proposed switch is the simplicity of control and high performance at both the call and cell levels. The switch meets the basic requirements that cells be delivered in the proper order, and that the rate of any individual connection can be as high as the inlet-port rate.