Low on-resistance high voltage thin layer SOI LDMOS transistors with stepped field plates

Abstract

We have proposed the concept of thin layer SOI devices with stepped field plates to obtain a low on-resistance LDMOSFET. Thin layer SOI devices can acquire a high breakdown voltage because the ionization integral over the vertical path may be neglected. A doping concentration in a drift region of a thin layer SOI device can be increased by reducing the thickness of the surface oxide. This is because the amount of induced charge increases by reducing the thickness of the oxide. The 600-V LDMOSFET was fabricated in line with the proposed concept and it accomplished the best trade-off among the LDMOSFETs reported so far (the breakdown voltage of 645 V and the specific on-resistance of 4.5 Ω·mm2).