Performance and Reliability Co-design of Ultra High Voltage LDMOS Devices

Abstract

This work presents the performance and re-liability (HCI, SOA and ESD) co-design insights of Ul-tra High Voltage (UHV) Laterally Diffused Metal Oxide Semiconductor (LDMOS) devices. Device design insights and performance optimization guidelines for four different types of UHV LDMOS devices (Conventional, RESURF, SOI and RESURF SOI) is systematically developed using 3D TCAD. For the first time, a step-by-step approach to design gate, drain and source field plates and its implications on the co-design of these four different UHV designs is investigated, which demonstrated significant improvement in the device breakdown without altering its ON-resistance. Finally, performance and HCI, ESD & SOA reliability benchmarking is done for the optimum designs of all four (i.e. Conventional, RESURF, SOI and RESURF SOI) UHV LDMOS architectures.