Manuel Potércau, N. Deltimple, A. Ghiotto, O. Jardel, S. Rochette, H. Leblond, J. Villemazet
{"title":"High-Reliability Active Integrated Power Limiter with Sharp Compression Profile in Ka-Band in 130 nm SiGe Technology","authors":"Manuel Potércau, N. Deltimple, A. Ghiotto, O. Jardel, S. Rochette, H. Leblond, J. Villemazet","doi":"10.23919/EuMIC.2019.8909462","DOIUrl":null,"url":null,"abstract":"A power limiter with high input power handling (24 dB over the input compression point) and sharp compression profile (less than 1.5 dB between the output 1-dB compression point and the output saturated power) in Ka-band (17.3 GHz; 20.2 GHz) is presented in this paper. Moreover, the circuit shows a low phase distortion (<3°) which make it suitable for use in an analog pre-processing linearizing system. This performances are obtained thanks to a novel architecture based on a power amplifier topology. This work presents the architecture along with the design methodology. Reliability is studied at high input power condition using the safe operation area from the technology provider. Then, a prototype is designed on 130 nm BiCMOS technology from STMicroelectronics, measured and compared to the simulation and the state of art.","PeriodicalId":228725,"journal":{"name":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 14th European Microwave Integrated Circuits Conference (EuMIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/EuMIC.2019.8909462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A power limiter with high input power handling (24 dB over the input compression point) and sharp compression profile (less than 1.5 dB between the output 1-dB compression point and the output saturated power) in Ka-band (17.3 GHz; 20.2 GHz) is presented in this paper. Moreover, the circuit shows a low phase distortion (<3°) which make it suitable for use in an analog pre-processing linearizing system. This performances are obtained thanks to a novel architecture based on a power amplifier topology. This work presents the architecture along with the design methodology. Reliability is studied at high input power condition using the safe operation area from the technology provider. Then, a prototype is designed on 130 nm BiCMOS technology from STMicroelectronics, measured and compared to the simulation and the state of art.