A 20-ps temperature compensated Time-to-Digital Converter (TDC) implemented in FPGA

Abstract

This paper presents a temperature compensation design for carry chain based Time-to-Digital Converter (TDC) in FPGA. The bin-by-bin calibrations under different temperatures are performed for both plain TDC and Wave Union TDC to characterize the influence of temperature variation on the delay time of carry chain which shows all TDC channels have the similar temperature-LUT coefficient. Accordingly, a simplified temperature compensation scheme by using a dedicated correction channel to measure the coefficient and correct fine time result for all TDC channels is implemented and tested. This method shows only few picosecond errors for both simulation and measurement. With this compensation approach, a 21ps RMS TDC resolution has been achieved in Cyclone II FPGA under a wide temperature range from 10°C to 75°C. Several design key points are also described in this paper.