J. N. Tripathi, G. Somani, K. Mundra, S. S. Verma, Hiren Joshi
{"title":"Soft-Reconfiguration Management for Operating Systems with Multiprocessor Architecture","authors":"J. N. Tripathi, G. Somani, K. Mundra, S. S. Verma, Hiren Joshi","doi":"10.1109/ADCOM.2007.113","DOIUrl":null,"url":null,"abstract":"sumer market to be prepared for business of new products everyday. With these tech-advancements, a new motherboard is designed for every release of a new processor in the form of fixed ASIC thus makes the old motherboards useless. This leads to two big problems of E-waste as well as Technology upgradation cost. To overcome these problem, authors have already proposed Three-Tier architecture for the computer processors that intro- duces a Reconfigurable Master Processor in FPGA, controling all other old technology processors. This uses a smart OS named kshtizindia1-OS (KIOS), at higher tier, Reconfigurable FPGA (Master Processor) at middle tier and the old processors at lower tier. This architecture emphasizes on an innovative concept of a very smart and auto-reconfigurable Operating System, KIOS with a reconfigurable CPU in FPGA that controls and reuses the old processors. The KIOS will incorporate the feature of soft-reconfiguration or auto-updation such that it can be able to reconfigure the FPGA as per the need of new release. All the tasks in the three tier architecture of KIOS is managed and interfaced for user by an application cum system software. Serially, these all tasks are presented here by a seven step process. This new architecture also contains new techniques of implementation for main memory, cache memory, bus architectures data and address mapping, multiprocessor scheduling and clock management. Index Terms-- E-wastage, Reconfigurable processor, Soft- reconfigurable Operating systems, Multiprocessor and Parallel architectures.","PeriodicalId":185608,"journal":{"name":"15th International Conference on Advanced Computing and Communications (ADCOM 2007)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"15th International Conference on Advanced Computing and Communications (ADCOM 2007)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ADCOM.2007.113","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
sumer market to be prepared for business of new products everyday. With these tech-advancements, a new motherboard is designed for every release of a new processor in the form of fixed ASIC thus makes the old motherboards useless. This leads to two big problems of E-waste as well as Technology upgradation cost. To overcome these problem, authors have already proposed Three-Tier architecture for the computer processors that intro- duces a Reconfigurable Master Processor in FPGA, controling all other old technology processors. This uses a smart OS named kshtizindia1-OS (KIOS), at higher tier, Reconfigurable FPGA (Master Processor) at middle tier and the old processors at lower tier. This architecture emphasizes on an innovative concept of a very smart and auto-reconfigurable Operating System, KIOS with a reconfigurable CPU in FPGA that controls and reuses the old processors. The KIOS will incorporate the feature of soft-reconfiguration or auto-updation such that it can be able to reconfigure the FPGA as per the need of new release. All the tasks in the three tier architecture of KIOS is managed and interfaced for user by an application cum system software. Serially, these all tasks are presented here by a seven step process. This new architecture also contains new techniques of implementation for main memory, cache memory, bus architectures data and address mapping, multiprocessor scheduling and clock management. Index Terms-- E-wastage, Reconfigurable processor, Soft- reconfigurable Operating systems, Multiprocessor and Parallel architectures.