An efficient optimal clock network buffer sizing with slew consideration

Abstract

One of the challenging stages in Very Large Scale Integration (VLSI) design is clock network synthesis that plays an important role in the circuit performance. Digital Integrated Circuits (IC) include synchronous components and timing criteria are the most important performance constraints in the VLSI designs. This paper describes an efficient optimal method to solve the clock network buffer sizing non-convex optimization problem. We use a geometric programming format with two competing objectives, power consumption and clock network skew considering slew and technology constraints to find the global optimal solution. The proposed formulation is applied on the latest clock network benchmarks from the 2009 and 2010 ISPD clock network contests and results show up to 86% reduction in power consumption and up to 183 ps skew reduction. We also show our proposed formulation can be solved efficiently in a relatively short runtime compared to other existing algorithms in the literature.