Investigation of Induced EFT Transient Noise and Effect on Chip and Package Level

Abstract

This paper investigates the noise induced from EFT Burst transient IEC61000-4-4 on the chip and package levels and analyzes its degradation effect. We first introduce the EFT Burst transient generator model previously established published with ANSYS Designer, which has later been adopted into ANSYS Electronics Desktop serving for immunity effect and protection measure analysis. We then describe how electromagnetic simulations can provide chip-level immunity analysis for IEC 62215-3. The analysis of EFT pulse propagation can be extended to package level with its impact on clock waveforms of different frequencies. With the help of established model, the residual transient noise energy due to normally found decoupling capacitor will be observed to show its effectiveness on noise filtering and the significant benefits to EMS protection. This study intends to provide an efficient simulation model to help IC and package designers enhancing their design capability against EFT disturbance.