Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) Pub Date : 2004-06-07 DOI:10.1109/IITC.2004.1345683

K. Lee, H.J. Shin, J.W. Hwang, S.W. Nam, Y.J. Moon, Y. Wee, I.G. Kim, W. Park, J.H. Kim, S.J. Lee, K.K. Park, H. Kang, K. Suh

引用次数: 3

Abstract

A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).

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高度可制造的铜/低钾双大马士革工艺集成为65nm技术节点

采用hsq -过孔填充双damascene工艺集成了可制造的Cu/低k多电平互连，用于65nm节点，如k - w所述。李等人(2003)。通过引入无沟槽刻蚀堵塞物和封盖氧化物的无孔型SiOC薄膜(k=2.7)，得到65nm设计规则下的有效k (keff)小于3.0。根据K.C. Park等人(2003)的研究，通过改进的单元工艺技术，如无损伤的覆盖氧化物、无磨料的低k直接抛光、先进的电离PVD (AiPVD)屏障金属和双层介电屏障等，实现了简单可靠的工艺。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

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