A very low-voltage differential amplifier for opamp design

F. Centurelli, P. Monsurrò, G. Scotti, A. Trifiletti
{"title":"A very low-voltage differential amplifier for opamp design","authors":"F. Centurelli, P. Monsurrò, G. Scotti, A. Trifiletti","doi":"10.1109/ECCTD.2011.6043846","DOIUrl":null,"url":null,"abstract":"In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter, that can give rise to some clock feedthrough in continuous-time applications. However good linearity with limited clock intermodulation can be achieved by careful design. An opamp in 65-nm CMOS technology featuring the proposed input stage is operational for supply voltages as low as 0.5 V, with a net linearity improvement with respect to a simple pseudo-differential stage.","PeriodicalId":126960,"journal":{"name":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 20th European Conference on Circuit Theory and Design (ECCTD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2011.6043846","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

Abstract

In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter, that can give rise to some clock feedthrough in continuous-time applications. However good linearity with limited clock intermodulation can be achieved by careful design. An opamp in 65-nm CMOS technology featuring the proposed input stage is operational for supply voltages as low as 0.5 V, with a net linearity improvement with respect to a simple pseudo-differential stage.
用于运放设计的极低压差分放大器
在本文中,我们提出了一种差分级,适合作为轨对轨极低压放大器的输入级。该拓扑利用输入移电平器来保持伪差分对的共模输入电压恒定,从而在整个输入共模范围内提供恒定增益。所提出的解决方案的主要缺点是需要一个开关电容电平移位器,这可能会在连续时间应用中产生一些时钟馈通。然而,良好的线性和有限的时钟互调可以通过精心设计来实现。采用65nm CMOS技术的运算放大器具有所提出的输入级,可在低至0.5 V的电源电压下工作,相对于简单的伪差分级,其净线性度有所提高。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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