F. Centurelli, P. Monsurrò, G. Scotti, A. Trifiletti
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引用次数: 8
Abstract
In this paper we present a differential stage suitable to be used as the input stage of rail-to-rail very low-voltage opamps. The topology exploits an input level-shifter to keep the common-mode input voltage of a pseudo-differential pair constant, thus providing a constant gain over the whole input common-mode range. The main drawback of the proposed solution is the need of a switched-capacitor level-shifter, that can give rise to some clock feedthrough in continuous-time applications. However good linearity with limited clock intermodulation can be achieved by careful design. An opamp in 65-nm CMOS technology featuring the proposed input stage is operational for supply voltages as low as 0.5 V, with a net linearity improvement with respect to a simple pseudo-differential stage.