A new preprocessing and control board for the phase 2 electronics of AGATA experiment

J. Collado, J. Blasco, N. Dosme, V. González, X. Grave, N. Karkour, X. Lafay, E. Legay, D. Linget, E. Sanchis
{"title":"A new preprocessing and control board for the phase 2 electronics of AGATA experiment","authors":"J. Collado, J. Blasco, N. Dosme, V. González, X. Grave, N. Karkour, X. Lafay, E. Legay, D. Linget, E. Sanchis","doi":"10.1109/RTC.2016.7543161","DOIUrl":null,"url":null,"abstract":"The electronics of AGATA HPGe segmented gamma ray detector faces a new challenge in the search of a bigger integration and cost reduction for the phase 2 of the experiment going beyond 45 crystals. This opportunity can be used to introduce a new architecture based on commercial standards while keeping backward compatibility with current electronics. In this sense, new FPGA devices and fast Ethernet links can be used to ease the preprocessing and control task and allowing for processor farms to distribute the processing load. At the same time, modularity should be a key feature of the design in the aim to make it upgradable in time and technology. This paper presents the design of a new preprocessing and control board that could fulfill with the experiment requirements having in mind that it should not be only a new system but also should serve as replacement of the current electronics. The design is intended to process the data coming from 3 crystals (114 channels) in the same board, with a total aggregate bandwidth of 216 Gpbs using 2 Gbps input optical fiber links in SNAP12 format and with a data readout done through Ethernet fiber optics. It is expected that, with this new system, the level of integration will raise up to 3 times while cost will scale down a 30% with respect to the current electronics.","PeriodicalId":383702,"journal":{"name":"2016 IEEE-NPSS Real Time Conference (RT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE-NPSS Real Time Conference (RT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RTC.2016.7543161","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

The electronics of AGATA HPGe segmented gamma ray detector faces a new challenge in the search of a bigger integration and cost reduction for the phase 2 of the experiment going beyond 45 crystals. This opportunity can be used to introduce a new architecture based on commercial standards while keeping backward compatibility with current electronics. In this sense, new FPGA devices and fast Ethernet links can be used to ease the preprocessing and control task and allowing for processor farms to distribute the processing load. At the same time, modularity should be a key feature of the design in the aim to make it upgradable in time and technology. This paper presents the design of a new preprocessing and control board that could fulfill with the experiment requirements having in mind that it should not be only a new system but also should serve as replacement of the current electronics. The design is intended to process the data coming from 3 crystals (114 channels) in the same board, with a total aggregate bandwidth of 216 Gpbs using 2 Gbps input optical fiber links in SNAP12 format and with a data readout done through Ethernet fiber optics. It is expected that, with this new system, the level of integration will raise up to 3 times while cost will scale down a 30% with respect to the current electronics.
一种用于AGATA实验第二阶段电子学的新型预处理和控制板
AGATA HPGe分段伽玛射线探测器的电子学面临着新的挑战,在超过45个晶体的实验第二阶段,寻求更大的集成度和降低成本。这个机会可以用来引入基于商业标准的新架构,同时保持与当前电子产品的向后兼容性。从这个意义上说,新的FPGA设备和快速以太网链路可以用来简化预处理和控制任务,并允许处理器群分配处理负载。同时,模块化应成为设计的一个重要特征,使其具有时间和技术上的可升级性。本文提出了一种新的预处理和控制板的设计,它不仅是一个新的系统,而且是现有电子设备的替代品,可以满足实验要求。该设计旨在处理来自同一板上3个晶体(114个通道)的数据,总总带宽为216 Gpbs,使用2gbps的SNAP12格式输入光纤链路,并通过以太网光纤完成数据读出。预计,与目前的电子产品相比,这种新系统的集成度将提高3倍,而成本将降低30%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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