Guard Band Minimization via Impedance Reduction and Dynamic Voltage Scheduling Schemes

Abstract

Voltage guard bands required to safeguard against load transient induced voltage undershoots result in power and performance penalties for high performance CPUs. This paper presents design techniques for impedance minimization and framework to dynamically alter sense and reference voltages based on information about distributed impedance, silicon speed, and scheduled load activity. Studies show guard band reduction by several tens of mV.