Low Leakage and High Speed Sub-threshold 128-bit Fin-FET SRAM for Ultra-Low-Power Applications

Abstract

The demand for Low power handheld devices are rapidly increasing in the recent past and memory is the heart of the processor. SRAM architecture of Fin-FETs is the most emerging design used for high computational designs functionality and performance near the sub-threshold region of operation. The demand for customer handheld equipment and rapid growth in technologies leads to high computational and innovative designs, especially in memory architectures. Traditional SRAM using CMOS designs that occupy the maximum area and high leakage power that leads to poor performance operating under a sub-threshold regime. PVT Variations, BTI, sizing, delay along with power consumption are some of the factors affecting performance. Switching is the primary factor that contributes to major leakage at the near-threshold region. The main objective of the proposed model is a literature survey to design a 128-bit FinFET-based SRAM architecture operating under a threshold region. The second objective is to analyze power, SNM, and delay. Comparative analysis of various effects on CMOS and Fin FinFET designs is done in the third objective. The final objective is framed on performance and functionality, and reliability to provide the trade tradeoff between CMOS Vs. FinFET designs.