Design of a Parallel Adder Circuit for a Heavy Computing Environment and the Performance Analysis of Multiplication Algorithm

J. Das, P. Choudhury, Sudhakar Sahoo
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引用次数: 1

Abstract

Firstly, this study proposed a new parallel adder circuit model in Carry Value Transformation (CVT)-Exclusive OR (XOR) paradigm. Secondly, an efficient multiplication algorithm is discussed along with its performance analysis on various inputs selection. Our design of proposed model for the addition of many integer pairs using parallel Cellular Automata Machines (CAMs) can perform the addition in a much better way with setting a preprocessing testing logic in it. CVT and XOR operations together can do the efficient addition of two non-negative integers for any bulk inputs using CAM. Multiplication is the repetitive addition process, which could be designed using recursive use of CAM. Our analysis up to 10 bits selection of all integer pairs suggest that the recursive use of CAM for multiplication becomes much faster in real life scenario for any types of inputs. Further exponential operation is highly needed for various fields of computer science which is also described in this paradigm.
大计算环境下并行加法器电路设计及乘法算法性能分析
首先,本文提出了一种新的进位值变换(CVT)-异或(XOR)并行加法器电路模型。其次,讨论了一种高效的乘法算法,并对其在不同输入选择下的性能进行了分析。我们提出的使用并行元胞自动机(CAMs)的整数对加法模型设计可以通过设置预处理测试逻辑以更好的方式执行加法。CVT和异或操作一起使用CAM可以对任何批量输入进行两个非负整数的有效相加。乘法运算是一种重复的加法运算过程,可以用CAM递归设计。我们对所有整数对的10位选择的分析表明,对于任何类型的输入,CAM的乘法递归使用在现实生活场景中都要快得多。进一步的指数运算是高度需要的计算机科学的各个领域,这也被描述在这个范式。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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