The miller effect in digital CMOS gates and power consumption analysis

Abstract

This paper deals with the Miller Effect occurrence in standard CMOS gates and possibility to take it into considerations during power dissipation analysis. Internal capacitances occurring in MOS transistors give the effect of capacitive coupling between input and output of the gate. It seems that the Miller theorem can be applied in a simplified approach to the analysis of energy and time in static CMOS gates. The main purpose of this paper is to discuss whether the Miller theorem can be effectively used in the analysis of energy and time in CMOS gates. What is the accuracy of such approach and what are the limitations? Theoretical considerations are supplemented by simulations.