An Efficient Approach of Power Reducing for Scratch-Pad Memory Based Embedded Systems

Abstract

Scratch-pad memory (SPM) is widely used in embedded systems. It is a topical and crucial subject to reduce power consumption for SPM systems, since high power consumption can reduce systems reliability and increase the cost and size of heat sinks. In this paper, we propose an effective approach of power reducing to scale down voltage and frequency as much as possible. We first pipelined data transference and processing. Second, we find the comparative time slack between fast data processing and low data transference, and then provide both single and dynamic scaling to reduce power consumption. We conduct our approach on the simulator of Trim ran, and the experimental results show that the approach achieves significant power reduction improvement while the run-time performance outperforms previous work.