Hardware efficient digital channeliser designs for radar intercept applications

Abstract

Radio frequency (RF) signal intercept systems, such as electronic support (ES) receivers, are inherently wideband by design to provide spectral surveillance over a wide frequency range. To meet both sensitivity and frequency coverage requirements, a digital channelised receiver architecture, such as that proposed in [1], is very attractive. An improved channeliser-synthesiser architecture, which provides continuous coverage of the receiver bandwidth, has also been proposed in [5] and we provide details of a design used by DSTO in its on-going development of an experimental ES Testbed. Despite their advantages, both of these receiver architectures have a fixed channel bandwidth that cannot provide optimal bandwidth reduction for the detection and processing of a diverse set of signals, such as that encountered in radar intercept applications. In this paper, a hardware efficient, cascaded channeliser architecture is proposed which allows a wideband radar intercept receiver to dynamically customise its channel bandwidth to the bandwidth of an intercepted signal in real-time.