A new sub-threshold 7T SRAM cell design with capability of bit-interleaving in 90 nm CMOS

Abstract

In this paper we present a new Static Random Access Memory (SRAM) that has 7 transistors in each cell. This idea allows for bit-interleaving that makes the SRAM more reliable against the soft errors. One of the challenges of a conventional 6 transistor (6T) SRAM cell in sub-threshold region is sizing of its access transistors. Here by separating access transistors of reading and writing, we mitigate this challenge. By using a minimum-size access transistor for reading, probability of unsuccessful read reduces. To have a more successful write operation, we make one of the inverters of the cell that is fighting with the write access transistor, weaker during write operation by floating its supply voltage and ground rails. After write operation, this inverter returns back to normal mode. Simulation results in 90 nm CMOS technology show that our design satisfies 4.5-sigma criterion for reading and writing at supply voltage of 300 mV. Compared to conventional 6T SRAM cell, our design improves read-time and write-time significantly. For example at supply voltage of 500 mV, these improvements are 137 and 83 percents, respectively. Comparing power and energy consumption for single write operation of the proposed 7T SRAM cell at supply voltage of 300mV with conventional 6T SRAM cell at 800mV (i.e. minimum achievable voltage for this SRAM cell) shows improvements of 133.4X and 266.78X, respectively.