A phase-based single-bit Delta-Sigma ADC architecture

Abstract

A Phase-based Delta-Sigma (ΔΣ) Analog-to-Digital Converter (ADC) adopting a Delay-Locked-Loop (DLL) mechanism is presented. It is realized by a modification of a DLL using a Voltage-Controlled Delay Line (VCDL) based quantizer and a charge pump in the feedback path. The proposed architecture offers both reference jitter shaping and quantization noise shaping. Simulation results show that the proposed ΔΣ ADC achieved 7.99 bits resolution with OSR =32 for a 10 MHz signal bandwidth.