A detailed capacitive analysis of symmetric and asymmetric dual-k FinFETs for improved circuit delay metrics

Abstract

In the past decade, high permittivity spacer materials has emerged as a potential performance booster in ultra scaled underlap devices to achieve better electrostatic control. However, the enhanced parasitic capacitance inherently associated with high-k materials poses several design challenges that limits its applicability to high-performance (HP) circuits. To improve the overall device performance, symmetric and asymmetric dual-k spacer FinFET architectures had been demonstrated. This paper briefly investigates the effect of the optimized symmetric and asymmetric dual-k structures for better logic circuit performance. This work demonstrates the suitability of high-k spacer materials for high-performance logic circuits improving delay metrics. Compared to the conventional FinFET, symmetric and asymmetric dual-k based inverter speed up the inverter circuit by 32% and 54.4 %, respectively for TiO2 (k=40) spacer materials, even though the total gate capacitance significantly increases by 2.1× and 3.2×, respectively.