Supercomputers and European Sovereignty ...

Abstract

Over that last 3 decades, we have witnessed a transition from closed software ecosystems being the foundation for HPC, enterprise, and business to open source software ecosystems based on Linux: from Arduino in the IoT space, to Android in the mobile space to Linux in HPC and cloud-based systems with various Open Source Software projects built on top. However, when examining hardware, current commercial off the shelf solutions are closed hardware ecosystems that only enable integration at the peripheral (PCIe) level. The combination of current technology trends, the slowing of Moore’s Law, and cost prohibitive silicon manufacturing inhibit significant power-performance gains by relying on traditional closed ecosystems, especially in HPC, technology pushed to the extreme. This new regime forces systems to be much more specialized to achieve the power-performance profiles required for a supercomputer. In the past, HPC has led the way forward, defining the bleeding edge of technology. HPC can do this again with open hardware, as it has done in software with adopting Linux and open source in general. This is not only a technology imperative, but one born out of current geopolitics. Digital Technology (the generation and processing of data) is the basis for global commerce, scientific discovery, and ubiquitous in modern life. Thus, creation of digital technology in the form of processors, accelerators and the related digital infrastructure guarantees access to these building blocks of the digital economy regardless of the geopolitical environment. Given this technology and geopolitical backdrop, we describe how Europe can exploit its resources targeting research and development for technological independence. from performance stack, Abstract Root Cause Analysis (RCA) and Layout Pattern Analysis (LPA) are critical technologies for Diagnosis Driven Yield Learning in designing and manufacturing integrated circuits. Recent advancements of AI technologies can help improving yield learning accuracy and transferring the yield learning experiences from old designs to new designs or from old technologies to the new ones. In this talk, we share our experiences in this research area and discuss the following techniques: Abstract The ever-increasing demands of high-performance visual and accelerated computing has resulted in GPUs becoming some of the most complex ASICs being built today. The last few years have also seen an explosion in demand for unique silicon designs serving varied markets such as gaming, HPC, healthcare, smart cities, robotics and automotive. Process scaling is an important factor of delivering such continuous performance gains over the decades. Some of these designs push the limits of current chip manufacturing technology, growing to 80B transistors and beyond. Furthermore, these new designs are implemented with innovative new methods in physical design and are accelerated to reach the market at a staggering pace. Delivering outgoing quality in such an expeditious development environment presents unique test challenges related to test time, cost, power, advanced defectivity and diagnosability to list a few. This talk will provide a summary of various ideas used at NVIDIA to tackle these challenges: Using functional high-speed interfaces for test-data transfer, portable test solutions, programmable test architectures, improved design-for-debug features, emulation for DFX, and using machine learning to solve DFX problems. Abstract In last decade, SiGe BiCMOS technologies open a new cost-efficient market first at mm-wave frequencies, then at sub-THz and THz range. Starting with the commercial use of automotive radars at 77 GHz, and the demand for 120/140 GHz radars, the market now has a strong interest on low-cost silicon based technologies for such high frequencies. The driving force behind the BiCMOS is not anymore only radar applications but also 5G/6G communication systems, operating at 60, 140 or even 240/300 GHz. Furthermore, the strong need on the driving circuitries of photonics components has created a mass market of high speed communication circuitries. The latest developments on SiGe HBTs with fmax of beyond 700 GHz boosts the research and development effort on circuit and system area to take share from the new markets. In parallel to the developments on SiGe HBT performance, “More-than-Moore” path, which covers all the additional functionalities to the standard CMOS process (i.e. MEMS devices, microfluidics, photonics, etc…), allows to realize multi-functional circuits and systems. Heterogeneous integration as a key and enabler multi-functional systems Hetero integration of different technologies such as high scaled CMOS, SiGe BiCMOS or even III-V ones has become real. Such integration of multi-chip technologies provides the highest performance with the most efficient size and power consumption; thus paves the way for next generation smart systems integration. In approaches used of different More-than-Moore modules into will be presented. New hetero-integration and