Bistable-Triplet STDP circuit without external memory for Integrating with Silicon Neurons

Abstract

Spiking Neural Network can adapt to the environment if it has the capacity to learn based on spike timing-dependent plasticity (STDP) by which the synaptic weight gets modified based on time difference between pre and postsynaptic spikes. The classical pair-based STDP model which considers only a pair of pre and post spikes has failed to account for synaptic activity when driven by a series of spikes. Whereas, Triplet based STDP model provides best fit for the experimental data as well as maps on to the Bienenstock-Cooper-Munro (BCM) learning rule. Implementation of plasticity rules at circuit level is necessary for realizing efficient computational very large scale integration (VLSI) systems which incorporates learning and memory functions. The analog VLSI implementation of TSTDP available in literature so far requires external circuitry to identify precise timing between two immediate successive pre and post spikes. The TSTDP circuit proposed in this paper is capable of identifying precise time difference between any two spikes, provides potentiation or depression based on sign and strength of the time difference, and also inherits the BCM rule when driven with Poisson spike trains. The circuit has been simulated in LTspice-XVII with the “TSMC 180nm” technology library.