A 40nm/65nm process adaptive low jitter phase-locked loop

Abstract

As the chip performance improved, low jitter PLL is getting more attention. The migration of process requires more stability of PLL among different processes. In this paper, by depressing the non-ideality of charge-pump and setting the two-stage control voltage of VCO, the noise performance of PLL is improved. The self-adaptive bandwidth technology is used to decrease the dependency between process and performance. The simulation proves that this PLL can adapt to both 40nm and 65nm process. The chip is taped out under 40nm CMOS process, the phase-noise performance of this PLL is -130dBc/Hz@3MHz at 1GHz, the maximum VCO output is up to 3.2GHz, the lowest resolution is 0.048Hz, which guarantees the high versatility and high performance of this PLL.