VMM emulation of Intel hardware transactional memory

ROSS@ICS Pub Date : 2014-06-10 DOI:10.1145/2612262.2612265
Maciej Swiech, Kyle C. Hale, P. Dinda
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引用次数: 2

Abstract

We describe the design, implementation, and evaluation of emulated hardware transactional memory, specifically the Intel Haswell Restricted Transactional Memory (RTM) architectural extensions for x86/64, within a virtual machine monitor (VMM). Our system allows users to investigate RTM on hardware that does not provide it, debug their RTM-based transactional software, and stress test it on diverse emulated hardware configurations, including potential future configurations that might support arbitrary length transactions. Initial performance results suggest that we are able to accomplish this approximately 60 times faster than under a full emulator. A noteworthy aspect of our system is a novel page-flipping technique that allows us to completely avoid instruction emulation, and to limit instruction decoding to only that necessary to determine instruction length. This makes it possible to implement RTM emulation, and potentially other techniques, far more compactly than would otherwise be possible. We have implemented our system in the context of the Palacios VMM. Our techniques are not specific to Palacios, and could be implemented in other VMMs.
英特尔硬件事务性内存的VMM仿真
我们描述仿真硬件事务性内存的设计、实现和评估,特别是在虚拟机监视器(VMM)中针对x86/64的Intel Haswell Restricted transactional memory (RTM)体系结构扩展。我们的系统允许用户在不提供RTM的硬件上调查RTM,调试基于RTM的事务软件,并在各种模拟硬件配置上对其进行压力测试,包括可能支持任意长度事务的潜在未来配置。最初的性能结果表明,我们能够比在完整的模拟器下实现大约60倍的速度。我们系统的一个值得注意的方面是一种新颖的翻页技术,它允许我们完全避免指令模拟,并将指令解码限制为仅确定指令长度所必需的。这使得实现RTM仿真以及潜在的其他技术成为可能,并且比其他方式更加紧凑。我们已经在Palacios VMM上下文中实现了我们的系统。我们的技术不是特定于Palacios的,可以在其他vmm中实现。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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