Streamline Ahead-of-Time SYCL CPU Device Implementation through Bypassing SPIR-V

Wenju He, Yilong Guo, Xinmin Tian, Hideki Saito, Wenwan Xing, Feng Zou, Chunyang Dai, Maosu Zhao, Haonan Yang
{"title":"Streamline Ahead-of-Time SYCL CPU Device Implementation through Bypassing SPIR-V","authors":"Wenju He, Yilong Guo, Xinmin Tian, Hideki Saito, Wenwan Xing, Feng Zou, Chunyang Dai, Maosu Zhao, Haonan Yang","doi":"10.1145/3585341.3585381","DOIUrl":null,"url":null,"abstract":"Here we present the design and implementation of our LLVM-based Ahead-Of-Time (AOT) SYCL CPU device without using SPIR-V, known as non-SPIRV CPU device. Our design of non-SPIRV CPU device is intended to highlight a general SYCL CPU implementation that aims for both debuggability and performance. Contributions: • Streamline compiler optimization pipeline by integrating kernel optimizations and transformations into LLVM C++ pipeline. • Eliminate SPIR-V IR generation during the CPU device code compilation and leverage LLVM IR from compiler front-end directly to reduce compilation overhead and preserve IR information including debug info, among LLVM passes.","PeriodicalId":360830,"journal":{"name":"Proceedings of the 2023 International Workshop on OpenCL","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 2023 International Workshop on OpenCL","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/3585341.3585381","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

Here we present the design and implementation of our LLVM-based Ahead-Of-Time (AOT) SYCL CPU device without using SPIR-V, known as non-SPIRV CPU device. Our design of non-SPIRV CPU device is intended to highlight a general SYCL CPU implementation that aims for both debuggability and performance. Contributions: • Streamline compiler optimization pipeline by integrating kernel optimizations and transformations into LLVM C++ pipeline. • Eliminate SPIR-V IR generation during the CPU device code compilation and leverage LLVM IR from compiler front-end directly to reduce compilation overhead and preserve IR information including debug info, among LLVM passes.
通过绕过SPIR-V,简化提前SYCL CPU设备实现
在这里,我们介绍了不使用spirv的基于llvm的提前(AOT) SYCL CPU设备的设计和实现,称为非spirv CPU设备。我们设计的非spirv CPU设备旨在突出一个通用的SYCL CPU实现,其目标是可调试性和性能。•通过将内核优化和转换集成到LLVM c++管道中,简化编译器优化管道。•在CPU设备代码编译期间消除SPIR-V IR生成,并直接从编译器前端利用LLVM IR,以减少编译开销,并在LLVM传递中保留包括调试信息在内的IR信息。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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