Design of high bit rate digital correlator

Abstract

The remote sensing satellites transmit the data in PCM (pulse code modulation) formatted mode while embedding a synchronization code word at regular intervals as a time marker for the receiver synchronization. The currently available correlator ICs (integrated circuits) has a bandwidth limitation up to 60 MHz. The paper discusses novel design technique adopted by the authors to design the high speed digital correlator that caters to the requirements of the remote sensing satellites, which are in the road map for the next decade. The multiplexing design approach helped in achieving the higher bandwidth of operation. The VLSI (very large scale integration) design methodology adopted, resulted in reducing the design cycle time, the design optimization techniques ushered in realizing the entire logic in a single 36 macro cell CPLD (complex programmable logic device). The system has been validated for operational use.