Determining Bit-Error Rate When Utilizing Series-Connected Inverters as a Communications Channel

Abstract

Synchronization in the AC-stacked PV-inverter topology has been shown utilizing powerline communication where a low-bandwidth synchronization signal is transmitted from the grid interface to a receiver in each inverter allowing the controls to obtain the necessary phase alignment to the grid voltage that allows for them to operate completely autonomously. The authors have been developing a channel model to describe the transmission and reception of this synchronization signal as it propagates down the powerline and the series connected power-electronic devices. This paper builds upon this model and examines the effects of the noise in the channel as it affects the reliability of the receiver to accurately determine if the synchronization signal is correct. Such reliability is key to the decentralized control of the AC-stacked PV-inverter topology. With the channel model that can determine the amount of transmitted current and the noise in the system, a power optimized transmission can be established that remains in an acceptable operating limit for reliability. Even though the results are for the AC-stacked PV-inverter architecture, the model is generalized enough for applicable for any series-connected power electronics.