Tabular method for evaluation of incomplete address decoding in microprocessor systems

Abstract

A tabular method is described which permits immediate evaluation of the consequences of incomplete address decoding in microprocessor systems. The method is easy to apply and aids microprocessor system design in several ways: (a) the minimal address decoding requirements for a given system can be readily determined (b) undesirable simultaneous addressing of more than one device is avoided (c) address ranges which are available for system expansion are immediately apparent (d) if the available ranges are inadequate, the required additional decoding is readily determined.