Select transistor modulated cell array structure test for EEPROM reliability

Abstract

A test structure consisting of a not addressable EEPROM cell array is presented together with the measurement methodology. Accurate information on the threshold voltage distribution of the cells in the array is obtained from the transfer characteristic measured under select transistor clamping bias. We discuss in detail the working principle and the different levels of approximation, presenting several results for early process/design reliability evaluation (bake retention, control gate stress, programming pulse optimisation).