Generation of partial FPGA configurations at run-time

Abstract

The paper presents a method for generating partial bitstreams on-line for use in systems with run-time reconfigurable FPGAs. Bitstream creation is performed at run-time by merging partial bitstreams from individual component modules. The process includes the capability to create connections between the modules by selection from a set of routes found during an off-line pre-processing step. Placement and interconnection of modules must follow a precise set of rules. While restricting the number of possible module arrangements, this approach allows bitstream creation to be performed with relatively few computational resources. Using a demonstration system with a Virtex-II Pro FPGA with a PowerPC 405 CPU, the process of creating at run-time a partial bitstream for 22% of the device area takes 24 ms.