Byte-serial convolvers

Abstract

It is shown that previously proposed bit-serial convolver schemes (with weights in parallel form), working with zero separation between samples, can be transformed into byte-serial input schemes with a comparable clock rate, thus affording an increase in sampling rate equal to the number of bits in each byte. This is achieved by adopting a modified carry save circuit. The proposed schemes are based on a modified version of serial-parallel multipliers and on the use of pre-computed multiples of the weights. The case of 2-bit bytes is fully developed. It is shown that the use of samples represented in a biased binary number system leads to schemes that are only slightly more complex than the corresponding bit-serial schemes. The bit rate is determined by the delays of a full adder and a flip-flop. The schemes are composed by a number of bit-slices and appear to be easily partitionable in identical cascaded modules suitable for a fault tolerant architecture and a WSI implementation.<>