DESIGN OF A PARALLEL INTERCONNECT BASED ON COMMUNICATION PATTERN CONSIDERATIONS

Abstract

An interconnects versatility is usually described by its ability to support a variety of algorithmic patterns based on the physical or logical embeddings within its topology that match the desired algorithmic patterns. However, most such embeddings are available on u discrete basis, though a particular algorithm may require a variety of embeddings during different phases of its operation. To provide for such varying embedded topology needs, we propose a simple and VLSI realizable interconnect structure, termed as a Union Graph (UG), which combines two discrete interconnects, with very individual and distinctive capabilities, through a union operation. We present the union of the binary deBruijn graph (BDG) and a Torus to demonstrate the effectiveness of this approach. The focus is on providing practical usability of the network for algorithmic support rather than on graph properties. We highlight the importance of communication aspects of different execution phases in designing an algo-rithmically specialized interconnect. A set of examples are used to demonstrate the UG's versatility for algorithmic support.