FPGA debugging by a device start and stop approach

Abstract

This paper presents an FPGA debugging methodology based upon a device start and stop (DSAS) approach. Using this approach, the design starts and stops a device under test (DUT) and saves the data to external memory without human interaction. The presented debugging circuit saves data on a trace buffer and once the trace buffer is full, it stops the DUT, saves the data to external memory through Ethernet and then starts the DUT again. Hence the quantity of the debug data is not limited. The contents stored on the external devices can be viewed by open-source waveform viewers or HDL simulators subsequently. The main benefits of the technique are an unlimited debug window, less use of scarce FPGA resources and no loss of debugging data. Neither an external emulation system nor user intervention is required to save the recorded data once the BRAMs are full.