On the physical design of butterfly networks for PRAMs

Abstract

The design of networks for massively parallel computers is strongly influenced by available technology. The network latency, critical for many applications, is significantly increased by packaging constraints, i.e. many connections between switches involving pad drivers or even line drivers. The authors concentrate on reducing those influences for a butterfly network related to Ranade's routing algorithm. Such a network is being implemented for a parallel RAM (PRAM) with 128 physical processors and 128 K logical processors. The required throughput makes it critical to use shared buses and improves the problem of space. While delays caused by switches can only be hidden by mapping many virtual processors to some physical ones, connection latency may be reduced by additional registers (shorter clock cycle time) and suitable mapping schemes (less space). Suitable clustering of processor modules and network parts may additionally decrease the network delay.<>