{"title":"A real-time video-image mapping using polygon rendering techniques","authors":"T. Ikedo","doi":"10.1109/MMCS.1997.609585","DOIUrl":null,"url":null,"abstract":"This work proposes a new hardware architecture for a video-mapping processor, a key technology for generation of realistic visual images in the multimedia age. The processor combines a polygon renderer, reverse-projection processor, video-pattern cache, pattern scaler, shading processor and pixel cache. Real-time mapping of refreshed video images into animated computer graphic images is performed in parallel with a 3.8 ns max/mapped pixel. The system is implemented in the Truga001 singlechip graphics processor of 940,000 gates in 0.3μ CMOS, developed at the University of Aizu. This paper describes the mechanism of video mapping, architecture and performance evaluation.","PeriodicalId":302885,"journal":{"name":"Proceedings of IEEE International Conference on Multimedia Computing and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE International Conference on Multimedia Computing and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MMCS.1997.609585","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This work proposes a new hardware architecture for a video-mapping processor, a key technology for generation of realistic visual images in the multimedia age. The processor combines a polygon renderer, reverse-projection processor, video-pattern cache, pattern scaler, shading processor and pixel cache. Real-time mapping of refreshed video images into animated computer graphic images is performed in parallel with a 3.8 ns max/mapped pixel. The system is implemented in the Truga001 singlechip graphics processor of 940,000 gates in 0.3μ CMOS, developed at the University of Aizu. This paper describes the mechanism of video mapping, architecture and performance evaluation.