A 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference

D. Cordova, P. Toledo, H. Klimach, S. Bampi, E. Fabris
{"title":"A 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference","authors":"D. Cordova, P. Toledo, H. Klimach, S. Bampi, E. Fabris","doi":"10.1109/LASCAS.2016.7451012","DOIUrl":null,"url":null,"abstract":"Electromagnetic Interference (EMI) degrades the performance of voltage and current references, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Postlayout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/° C, for the temperature range from -55 to 125 ° C. An EMI source of 4 dBm (1 Vpp) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum DC Shift and Peak-to-Peak ripple of -0.17 % and 822 μVpp, respectively.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS.2016.7451012","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

Electromagnetic Interference (EMI) degrades the performance of voltage and current references, due to its finite Power Supply Rejection Ratio (PSRR). The design of a 90 dB PSRR, 4 dBm EMI resistant MOSFET-Only Voltage Reference is herein presented. The Voltage Reference is designed based on the Zero Temperature Coefficient (ZTC) transistor point. The high-PSRR is obtained using zero-VT transistors as active loads in the open and feedback loop of the circuit. The final circuit was designed in a 130 nm CMOS process and occupies around 0.014 mm2 of silicon area while consuming just 1.15 μW. Postlayout simulations present a 206 mV of Voltage Reference with a Temperature Coefficient of 321 ppm/° C, for the temperature range from -55 to 125 ° C. An EMI source of 4 dBm (1 Vpp) injected in the power supply, according to the Direct Power Injection (DPI) standard, yield in a maximum DC Shift and Peak-to-Peak ripple of -0.17 % and 822 μVpp, respectively.
一个90db PSRR, 4dbm耐EMI的mosfet基准电压
电磁干扰(EMI)由于其有限的电源抑制比(PSRR)而降低了电压和电流基准的性能。本文介绍了一种90db PSRR, 4dbm耐EMI的mosfet基准电压的设计。基准电压是基于晶体管零温度系数(ZTC)点设计的。在电路的开环和反馈回路中,采用零vt晶体管作为有源负载,获得了高psrr。最终电路采用130 nm CMOS工艺设计,硅面积约为0.014 mm2,功耗仅为1.15 μW。在-55 ~ 125℃的温度范围内,采用206mv基准电压,温度系数为321 ppm/°C,根据直接功率注入(DPI)标准,在电源中注入4 dBm (1 Vpp)的EMI源,产生的最大直流位移和峰间纹波分别为- 0.17%和822 μVpp。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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